1. Field of the Invention
Generally, the present invention relates to the fabrication of integrated circuits, and, more particularly, to metrology techniques that enable the estimation of dopant profiles in active semiconductor regions, such as the drain and source regions of field effect transistors.
2. Description of the Related Art
In the semiconductor industry, there is an ongoing tendency to continuously reduce the feature sizes of circuit elements so as to improve device performance and package density. A major fraction of today""s produced integrated circuits are digital devices manufactured by the so-called MOS technology, which involves the fabrication of a huge number of field effect transistor elements, substantially acting as switches. In these transistor elements, a lightly doped channel region separates inversely heavily doped source and drain regions, wherein a gate electrode controlling the formation of a channel in the channel region upon application of an appropriate control voltage is located above the channel region and separated therefrom by a thin insulation layer. The interface between the drain or the source region and the inversely lightly doped channel region forms a PN junction, wherein especially the shape and dimension of that portion of the PN junction connecting the drain or source region to the channel is of great importance to the transistor performance. Moreover, the distance between the source and drain region, also referred to as channel length, is a critical design parameter of the field effect transistor, as the channel length substantially affects the current capability and the switching speed of the transistor device.
During the last decade, the device dimensions of these field effect transistors have been steadily decreased to channel lengths of 0.1 xcexcm and even less, thereby improving the device performance while at the same time merely requiring modest power consumption when integrated CMOS circuits are considered. Therefore, this type of circuit architecture has become the dominant technology for integrated circuits. In steadily decreasing the feature sizes of transistor elements, one major issue is the formation of doped regions having well-defined shapes and dimensions so as to achieve a required dopant profile within these regions. As these dopant profiles substantially determine the charge carrier distribution, as well as the distribution of the electrical field prevailing in the device during its operation, strictly controlling the dopant profiles is essential to obtain superior device performance. Especially for extremely scaled circuits with dimensions in the deep sub-micron regime, additional problems arise that were unknown so far for transistor elements of the 1 micron range, so that even stricter constraints are imposed on the formation of appropriate dopant profiles.
In sophisticated transistor elements, the dopant profile has to be controlled in at least two dimensions, that is, in a depth direction with respect to a substrate carrying the circuit element and a direction perpendicular to the depth direction, which may also be referred to as lateral direction, to provide for the required charge carrier and field distribution. Since conventional diffusion techniques usually do not allow the formation of a specified dopant profile in a direction facing away from a dopant donating material layer, except for a gradually decreasing dopant concentration due to the nature of the diffusion process, implantation of ions has become the preferred technique for incorporating dopant atoms in a desired concentration at a desired depth of a specified region. The lateral profile or confinement of implanted dopant is usually achieved by forming respective implantation masks that may shield the underlying regions, partially or completely, thereby generating the required lateral profile. Although ion implantation enables the formation of a dopant concentration peak within reasonably restricted device regions, the final shape and dimension of the dopant profile is nevertheless partially determined by diffusion processes, ie., heating processes, that are necessary for activating the dopant atoms, i.e., to place the-dopant atoms at regular lattice sites, and to cure, at least partially, implantation-induced crystal damage.
In highly advanced transistor elements, the dimensions of the doped regions, for example, the source and drain regions with the channel region disposed therebetween, are extremely small and will be reduced in future device generations, so that the process margins in the implantation and the anneal, i.e., the diffusion processes, are continuously becoming more restricted. Therefore, reliable and efficient metrology techniques are required to steadily monitor the dopant profiles obtained by the implantation and anneal processes employed. For this reason, great efforts are being made to develop techniques to obtain information on dopant profiles within circuit elements. It turns out that the dopant concentration in the depth direction may be measured with very high accuracy, whereas substantially no information may be gathered relating to the lateral dopant profile, which is however essential for the functionality of the transistor element. Accordingly, a plurality of metrology techniques have been developed to more or less determine a two-dimensional image of the charge carrier distribution and thus of the dopant profile that is strongly related to the charge carrier distribution measured during the operation of the device. Respective techniques may include scanning capacitance microscopy (SCM), nano-spreading resistance profiling (nano-SRP), atomic force microscopy etch analysis or transmission electron microscopy etch analysis, scanning Kelvin probe force microscopy, and the like. Some of these techniques may provide a spatial resolution of approximately 10 nm as is considered necessary for current and future device generations. Most of these techniques are presently not approved under practical conditions and are still under research so that respective tools having high resolution and accuracy are presently not commercially available. Additionally, the techniques specified above require high effort in terms of sample preparation and tool handling, thereby significantly slowing down the development and testing of new technologies in forming dopant profiles of future device generations.
In view of the problems identified above, there is a need for an improved technique for determining lateral charge carrier and/or dopant profiles in circuit elements.
The present invention is directed to a technique to assess the lateral dimension of a dopant profile by determining an overlap capacitance of the profile in a structure forming a xe2x80x9ccapacitor,xe2x80x9d wherein the overlap capacitance is compared to a xe2x80x9creferencexe2x80x9d capacitance.
In one illustrative embodiment of the present invention, a method comprises identifying a relationship between a capacitive coupling of a conductor and a doped region formed in a semiconducting substrate tinder the conductor based upon an overlap between the conductor and the doped region. A second doped region is formed under a second conductor and a lateral dimension of an overlap of the second doped region with the second conductor is assessed based upon the identified relationship.
According to another illustrative embodiment of the present invention, a method comprises determining a first capacitive coupling of a reference dopant profile formed in a first semiconductor region to a first conductive region laterally offset from the reference dopant profile by a first dielectric region having a first offset thickness. The method further comprises determining a second capacitive coupling of the reference dopant profile formed in a second semiconductor region to a second conductive region laterally offset from the reference dopant profile by a second dielectric region having a second offset thickness. Moreover, a capacitive coupling of a test dopant profile is determined that is formed in a third semiconductor region to a third conductive region laterally offset from the third semiconductor region by a third dielectric region having a predefined offset thickness. Finally, a lateral distribution of the test dopant profile is assessed on the basis of the first and second capacitive couplings and the first, second and predefined offset thicknesses.
According to a further illustrative embodiment of the present invention, a method of assessing an implanted dopant profile comprises forming a first gate electrode structure with a first sidewall spacer having a first width and forming a second gate electrode structure with a second sidewall spacer having a second width. Then, a dopant profile is formed adjacent to the first and second gate electrode structure with substantially the same process conditions and using the first and second sidewall spacers as an implantation mask, each dopant profile acting as source and drain of a first transistor and a second transistor. Finally, an overlap capacitance of the first and second transistor is determined to establish a dependence of overlap capacitance variation with spacer width variation for the dopant profile.